View HCPL-810J_1247800.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Agilent HCPL-810J PLC Powerline DAA IC
Data Sheet
Description The HCPL- 810J is a galvanically isolated Powerline Data Access Arrangement IC. It provides the key features of isolation, Tx line driver and Rx amplifier as required in a powerline modem application. Used together with a simple LC coupling circuit, the HCPL- 810J offers a highly integrated, cost effective Analogue Front End (AFE) solution. Optical coupling technology provides very high isolation mode rejection, facilitating excellent EMI and Connection Diagram
TX-EN TX Powerline Transceiver IC (ENDEC) RX STATUS VCC1 1 2 3 4 5 6 7 8
EMC performance. Application robustness is enhanced by the inherent properties of optoisolation devices, to effectively block the transfer of damaging surge transients. Excellent transmitter performance is achieved with the use of a high efficiency, low distortion line driver stage. Transmitter robustness is further enhanced with integrated load detection and over- temperature protection functions. The HCPL- 810J is designed to work with various transceiver ICs and significantly simplify the implementation of a powerline modem.
Features * Highly Efficient Tx Line Driver * Built-in Rx Amplifier * Load Detection Function * Under-Voltage Detection * Over-Temperature Shutdown * Temperature Range: -40C to +85C * Regulatory Approvals (pending): UL, CSA, IEC/EN/DIN EN 60747-5-2 Applications * Automatic Meter Reading (AMR) * Powerline Modem * Home Automation/Control * Security and Surveillance * General Purpose Isolated Transceiver * Internet Appliances
Tx-en Tx-in Rx-PD-out Rx-Amp-in Status Rx-out VCC1 GND1 HCPL-810J
GND2 Tx-out VCC2 Tx-PD-out Tx-LD-in Cext Rx-in Rref
16 15 14 13 12 11 10 9
GND2
VCC2
Filter GND2 Filter L
N GND1 GND2 GND2
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Block Diagram
- -out Tx-PD 13 Tx-en 1 AGC G T2 15 Tx-out - -in Tx-LD 12
Tx-in -
2
Tx LED Driver Shield
Tx TIA
V CC1
7
Tx-en Detection Over -Temp Detection
Line Driver Control
14
V CC2
16
GND2
GND1
8
Control IC V CC2 UVD Load Detection 11 C ext
Status
5
Status Detection Rx TIA G R2 Shield 4 Rx -Amp-in 3 Rx -PD -out -Rx LED Driver
Status Logic
9
R ref
Amp
10
Rx -in
Rx -out -
6
Line IC
Pin Descriptions Package Pin Out Pin No. 1
1 2 3 4 5 6 7 8
Symbol Tx-en Tx-in Rx-PD-out Rx-Amp-in Status Rx-out VCC1 GND1 Rref Rx-in Cext Tx-LD-in Tx-PD-out VCC2 Tx-out GND2
Description Transmit Enable Input Transmit Input Signal Rx Photodetector Output Receiver Output Amplifier Input Signal indicating Line Condition Receiving Signal Output 5 V Power Supply VCC1 Power Supply Ground Sets Line Driver biasing current, typically 24 k Receiving Signal Input from Powerline External Capacitor Tx Line Driver Input Tx Photodetector Output 5 V Power Supply Transmit Signal Output to Powerline VCC2 Power Supply Ground
Tx -en Tx -in Rx -PD -out Rx -Amp -in Status Rx -out V CC1 GND1
GND2
16
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Tx -out 15 V CC2
14
Tx -PD -out 13 Tx -LD -in 12 C ext 11 Rx -in 10 R ref
9
2
Ordering Information Specify part number followed by option number (if desired). Example: HCPL-810J-XXX
No option = 16-Lead, Surface Mt. package, 45 per tube. 500 = Tape and Reel Packaging Option, 850 per reel.
Option data sheets available. Contact Agilent Technologies sales representative, authorized distributor, or visit our WEB site at www.agilent.com/view/optocouplers. Package Outline Drawings 16-Lead Surface Mount
0.018 (0.457) 16 15 14 13 12 11 10 9 0.050 (1.270) TYPE NUMBER DATE CODE
A 810J YYWW
0.295 0.010 (7.493 0.254) NOTES: 1. INITIAL AND CONTINUED VARIATION IN THE COLOR OF THE HCPL-810J's WHITE MOLD COMPOUND IS NORMAL AND DOES NOT AFFECT DEVICE PERFORMANCE OR RELIABILITY. 2. FLOATING LEAD PROTRUSION IS 0.006 (0.15) MAX. 0.345 0.010 (8.986 0.254)
1
2
3
4
5
6
7
8
0.406 0.10 (10.312 0.254) 9
ALL LEADS TO BE COPLANAR 0.002
0.018 (0.457)
0.138 0.005 (3.505 0.127)
0-8 0.025 MIN. 0.408 0.010 (10.160 0.254)
0.008 0.003 (0.203 0.076) STANDOFF
DIMENSIONS IN INCHES (MILLIMETERS).
Land Pattern Recommendation
0.458 (11.63)
0.085 (2.16)
0.025 (0.64)
DIMENSIONS IN INCHES (MILLIMETERS)
3
Package Characteristics All specifications and figures are at the nominal (typical) operating conditions of VCC1 = 5 V, GND1 = 0 V, VCC2 = 5 V, GND2 = 0 V and TA = +25C. Parameter Control IC - Line IC Momentary Withstand Voltage Resistance (Control IC - Line IC) Capacitance (Control IC - Line IC) Symbol VISO RI-O CI-O Min. 3750 >109 1.4 83 85 Typ. Max. Units Vrms pF C/W Test Conditions RH< 50%, t = 1 min., TA = 25C VI-O = 500 Vdc f = 1 MHz 1 oz. trace, 2-layer 4 PCB, Still air, TA = 25C Note 1, 2, 3 3
Control IC to Ambient Thermal Resistance IA Line IC to Ambient Thermal Resistance OA
Notes:
1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit, II-O 5 A). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable. 2. The Control IC-Line IC Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as a Control IC-Line IC continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table. 3. Device is considered as a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together. 4. Maximum power dissipation in Control side and Line side IC's needs to be limited to ensure that their respective junction temperature is less than 125C. The maximum permissible power dissipation is dependent on the thermal impedance and the ambient temperature. Details on the typical thermal impedances are given in the Package Characteristics. Further details on applying this to an actual application can be found in the Application Information section under Thermal Considerations.
Solder Reflow Temperature Profile 300
PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C PEAK TEMP. 230C 2.5C 0.5C/SEC. 160C 150C 140C 3C + 1C/-0.5C 30 SEC. 30 SEC. SOLDERING TIME 200C
TEMPERATURE (C)
200
100
PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE
0
0
50
100 TIME (SECONDS)
150
200
250
ROOM TEMPERATURE
4
Regulatory Information The HCPL-810J is pending for approval by the following organizations: IEC/EN/DIN EN 60747- 5- 2 UL CSA Approved under CSA Acceptance Notice #5, File CA 88324.
Recognized under UL 1577, Approved under: component recognition program, IEC 60747-5-2:1997 + A1:2002 File E55361. EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01 with VIORM = 891 Vpeak.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics (1) Description Installation classification per DIN VDE 0110/1.89, Table 1 For rated mains voltage 150 Vrms For rated mains voltage 300 Vrms For rated mains voltage 600 Vrms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b (2) VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a (2) VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Over-voltage (2) (Transient Over-voltage tini = 10 sec) Safety-limiting values - maximum values allowed in the event of a failure Case Temperature Control Side Power (3) Line Side Power (3) Insulation Resistance at TS, VIO = 500 V
Notes: 1. Isolation characteristics are guaranteed only within the safety maximum ratings that must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO802.
PS - POWER - mW
1600 1400 1200 1000 800 600 400 200 0 0 25 50 75 100 125 150 175 200 PS, OUTPUT PS, INPUT
Symbol
Characteristic I - IV I - III I - II 55/100/21 2
Unit
VIORM VPR
891 1670
VPEAK VPEAK
VPR
1336
VPEAK
VIOTM TS PS, INPUT PS, OUTPUT RS
6000 175 400 1500 >109
VPEAK C mW mW
2. Refer to the optocoupler section of the Isolation and Control Component Designer's Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles. 3. Refer to the following figure for dependence of PS, INPUT and PS, OUTPUT on case temperature.
TS - CASE TEMPERATURE - C
5
Insulation and Safety Related Specifications Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Symbol L(101) L(102) Value 8.3 8.3 0.5 Unit mm mm mm Condition Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance of conductor to conductor, usually the straight-line distance between the emitter and detector. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
>175 IIIa
Volts
Absolute Maximum Ratings Parameter Storage Temperature Ambient Operating Temperature Junction Temperature Supply Voltage 1 Supply Voltage 2 Transmit Output Voltage Transmit Input Signal Voltage Transmit Enable Voltage Receiving Input Signal Voltage Control-Side Power Dissipation Line-Side Power Dissipation Solder Reflow Temperature Profile
Notes: 1. Maximum power dissipation in Control side and Line side IC's needs to be limited to ensure that their respective junction temperature is less than 125C. The maximum permissible power dissipation is dependent on the thermal impedance and the ambient temperature. Details on the typical thermal impedances are given in the Package Characteristics. Further details on applying this to an actual application can be found in the Application Information section under Thermal Considerations.
Symbol TS TA TJ VCC1 VCC2 VTx-out VTx-in VTx-en VRx-in PI PO
Min. -55 -40 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5
Max. 125 85 125 5.5 5.5 VCC2 VCC1 VCC1 VCC2 200 1000
Unit C C C V V V V V V mW mW
Note
1
(See Solder Reflow Temperature Profile Section)
Recommended Operating Conditions Parameter Ambient Operating Temperature Input Supply Voltage Output Supply Voltage Tx-in Signal Current
Notes: 1. The transmitter input impedance is very low, this is meant for signal current input. Transmitter performance is optimized at 250 APP input signal, an external series resistor with nominal value of 2 k would be required if the input signal is 0.5 VPP.
Symbol TA VCC1 VCC2 ITx-in
Min. -40 4.75 4.75
Typ. 5 5 250
Max. 85 5.25 5.25
Unit C V V APP
Note
1
6
Electrical Specifications Unless otherwise noted, for sinusoidal waveform input and reference resistor Rref = 24 k, all typical values are at TA = 25C, VCC1 = 5 V, VCC2 = 5 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. General Parameter VCC1 Supply Current VCC2 Supply Current Status Logic High Output Status Logic Low Output Junction Over-Temperature Threshold Load Detection Threshold Isolation Mode Rejection Ratio
Notes: 1. Threshold of falling VCC2 with hysteresis of 0.15 V (typ.). 2. Threshold of rising junction temperature with hysteresis of 15C (typ.). 3. IMRR is defined as the ratio of the signal gain (measured at Rx-PD-out with signal applied to Rx-in) to the isolation mode gain (measured at Rx-PD-out with Rx-in connected to GND2 and the isolation mode voltage, VIM, applied between GND1 and GND2), expressed in dB.
Symbol Min. ICC1 ICC2 VOH VOL 3.8 VCC1-1
Typ. 6 20 22 40
Max. 20 35 30 70 1
Unit mA mA mA mA V V V C APP dB
Test Condition VTx-en = 0 V VTx-en = 5 V VTx-en = 0 V VTx-en = 5 V IOH = -4 mA VCC2 = 3.5 V, IOL = 4 mA
Fig. 1 1 2 2, 3, 4
Note
VCC2 Under Voltage Detection VUVD Tth
4 130 0.6
4.3
1 2 VTx-en = 5 V, f = 132 kHz VTx-en = 0 V, f = 132 kHz 5, 13 6, 14 3
IMRR
80
7
Electrical Specifications (Cont.) Unless otherwise noted, for sinusoidal waveform input and reference resistor Rref = 24 k, all typical values are at TA = 25C, VCC1 = 5 V, VCC2 = 5 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Transmitter Parameter Symbol Min. 0.8 10 180 2.8 3.3 3.6 Typ. Max. 2.4 Unit V s s VPP VTx-en = 5 V, ITx-in = 250 APP, f = 132 kHz, Tx-PDout no load VTx-en = 5 V, ITx-in = 250 APP, f = 132 kHz, TA = 25C VTx-en = 5 V, ITx-in = 250 APP VTx-en = 5 V, f = 132 kHz 15 1 2 7, 8, 9 Test Condition Fig. Note
Transmit Enable Threshold Volt- Vth, Tx-en age Set-up Time (Tx-PD-out) AGC Settling Time Tx Photodetector Output Voltage (Tx-PD-out) Bandwidth (Tx-PD-out) BWTxPD ts, Tx tAGC
1 1
MHz
Tx Photodetector Output Imped- ZO, TxPD ance (Tx-PD-out) Line Driver (LD) Power Supply (VCC2) Rejection Ratio Input Impedance DC Biased Voltage Gain PSRR ZI, LD VBias, LD GT2 1.8
55 10 2.27 2 -60 -65 0.5 7.5 2 2.2
dB k V V/V dB dB k APP
50 Hz ripple, Vripple = 200 mVPP VTx-en = 5 V, f = 132 kHz VTx-en = 5 V VTx-en = 5 V, f = 132 kHz, Tx-out no load, TA = 25C VTx-en= 5 V, VTx-out= 3.6 VPP, f=132 kHz, Tx-out load 50, TA=25C VTx-en = 5 V, f = 132 kHz VTx-en = 0 V, f = 132 kHz VTx-en = 5 V, VTx-LD-in = 1.8 VPP, f = 132 kHz, tP 50 s 3, 4 10
2nd Harmonic Distortion (Tx-out) HD2LD 3rd Harmonic Distortion (Tx-out) HD3LD Output Impedance (Tx-out) Short-Circuit Output Current
Notes:
ZO, LD IOS
1. Time from transmit is enabled (VTx-en is set to logic high) until output (Tx-PD-out) is available. See Figure 18 in the Application Information section. 2. Time from output (Tx-PD-out) is available until Tx-PD-out signal reaches 66% of its steady state level. See Figure 18 in the Application Information section. 3. To keep the junction temperature as close to the ambient temperature as possible, pulse testing method is used. The device is transmit-enabled within the pulse duration time, tP. Thermal effects must be considered separately. 4. Maximum power dissipation in Control side and Line side IC's needs to be limited to ensure that their respective junction temperature is less than 125C. The maximum permissible power dissipation is dependent on the thermal impedance and the ambient temperature. Details on the typical thermal impedances are given in the Package Characteristics. Further details on applying this to an actual application can be found in the Application Information section under Thermal Considerations.
8
Electrical Specifications (Cont.) Unless otherwise noted, for sinusoidal waveform input and reference resistor Rref = 24 k, all typical values are at TA = 25C, VCC1 = 5 V, VCC2 = 5 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Receiver Parameter Input Impedance Output Impedance (Rx-PD-out) Input Referred Noise Bandwidth (Rx-PD-out) Gain Set-up Time (Rx-PD-out) DC Biased Voltage Output Impedance Gain Bandwidth Product Symbol ZI, Rx ZO, RxPD Vnr BWRxPD GR1 ts, Rx VBias, Rx ZO, RxA GBWRxA Min. Typ. 4 30 70 500 20 10 2.27 20 28 Max. Unit k Test Condition VTx-en = 0 V, f = 132 kHz VTx-en = 0 V, f = 132 kHz Fig. Note
nV/ Hz VTx-en = 0 V, VRx-in = 0 VPP kHz VTx-en = 0 V dB VTx-en = 0 V, VRx-in = 0.05 VPP, f = 132 kHz s V MHz VTx-en = 0 V, f = 132 kHz VTx-en = 0 V, f = 132 kHz
11
Receiver Output Amplifier (RxAMP)
VTx-en = 0 V, f = 132 kHz, 12 VRx-in = 0.1 VPP, GR2 = -20, feedback resistor 20 k
9
Typical Performance Plots Unless otherwise noted, all typical plots are at TA = 25C, VCC1 = 5 V, VCC2 = 5 V, sinusoidal waveform input, signal frequency f = 132 kHz, ITx-in = 250 APP, and Rref = 24 k.
25
45 40
ICC1 - SUPPLY CURRENT - mA
20
ICC2 - SUPPLY CURRENT - mA
35 30 25 20 15 10 5 0 -50 -25 0 25 50 Rx Tx 75 100
15
10
5 Rx Tx 0 -50 -25 0 25 50 75 100
TA - AMBIENT TEMPERATURE - C
TA - AMBIENT TEMPERATURE - C
Figure 1. VCC1 supply current vs. temperature.
100 90
ICC2 - SUPPLY CURRENT - mA
Figure 2. VCC2 supply current vs. temperature.
300
80 70 60 50 40 30 20 10 0 5 10 15
ICC2 - SUPPLY CURRENT - mA
VTx-en = 5 V
250 200 150 100 50 0
20
25
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Rref - REFERENCE RESISTOR - kU
ITx-out - Tx-out OUTPUT CURRENT - APP
Figure 3. VCC2 supply current vs. reference resistor.
1.4 1.3
NORMALIZED AT 25C
Figure 4. VCC2 supply current vs. Tx output current.
90 85 80 75 70 65 60 55 50 0 0.5 1 1.5 2 f - FREQUENCY - MHz
1.2 1.1 1 0.9 0.8 0.7 0.6 -50
-25
0
25
50
75
100
TA - AMBIENT TEMPERATURE - C
Figure 5. Normalized load detection threshold vs. temperature.
10
ISOLATION MODE REJECTION RATIO - dB
Figure 6. Isolation mode rejection ratio vs. frequency.
Typical Performance Plots (Cont.) Unless otherwise noted, all typical plots are at TA = 25C, VCC1 = 5 V, VCC2 = 5 V, sinusoidal waveform input, signal frequency f = 132 kHz, ITx-in = 250 APP, and Rref = 24 k.
VTx-PD-out - Tx-PD-out OUTPUT VOLTAGE - VPP
-25 0 25 50 75 100 1.6 1.4
4
NORMALIZED AT 25C
3
1.2 1 0.8 0.6 0.4 -50
2
1
0 0 50 100 150 200 250 ITx-in - Tx INPUT CURRENT - APP
TA - AMBIENT TEMPERATURE - C
Figure 7. Normalized Tx-PD-out output voltage vs. temperature.
1.2 ITx-in = 65 APP 1
NORMALIZED AT 132 kHz
Figure 8. Tx-PD-out output voltage vs. Tx-in input current.
1.01
0.8 0.6 0.4 0.2 0 10 k
NORMALIZED AT 25C
1.005
1
0.995
100 k
1M
10 M
0.99 -50
-25
0
25
50
75
100
f - FREQUENCY - Hz
TA - AMBIENT TEMPERATURE - C
Figure 9. Normalized Tx-PD-out output voltage vs. frequency.
1.2 VRx-in = 50 mVPP 1
NORMALIZED AT 132 kHz
Figure 10. Normalized line driver gain vs. temperature.
120 110 GAIN PHASE 240 220 200 180 160 140 120 100 80 60 40 20 10 100 1k 10 k 100 k 1M 0 10 M
AOL - RxAMP VOLTAGE GAIN - dB
100 90 80 70 60 50 40 30 20 10 0
0.8 0.6 0.4 0.2
0 10 k
100 k
1M
10 M
f - FREQUENCY - Hz
f - FREQUENCY - Hz
Figure 11. Normalized Rx-PD-out output voltage vs. frequency.
Figure 12. RxAMP gain and phase vs. frequency.
PHASE - DEGREES
11
Test Circuit Diagrams Unless otherwise noted, all test circuits are at TA = 25C, VCC1 = 5 V, VCC2 = 5 V, sinusoidal waveform input, and signal frequency f = 132 kHz.
VCC1 1 2 3 4 SCOPE 5 6 VCC1 100 nF GND1 7 8 Tx-en Tx-in Rx-PD-out Rx-Amp-in Status Rx-out VCC1 GND1 HCPL-810J GND2 Tx-out VCC2 Tx-PD-out Tx-LD-in Cext Rx-in Rref 16 15 1 F 14 13 12 11 10 100 nF 9 Rref 24 k GND2 100 nF VIN = 1.5 VPP 1 F GND2 2. 5 RL GND2
VCC2 100 F
100 nF
Figure 13. Load detection test circuit.
GND1 VOUT SCOPE 100 nF 1 k GND1 VCC1 100 nF 1 2 3 4 5 6 7 8 Tx-en Tx-in Rx-PD-out Rx-Amp-in Status Rx-out VCC1 GND1 HCPL-810J GND2 Tx-out VCC2 Tx-PD-out Tx-LD-in Cext Rx-in Rref 16 15 14 13 12 11 1 F 10 100 nF 9 Rref 24 k 5V 100 nF 100 F
VIM = 10 VPP GND1 GND2
Figure 14. Isolation mode rejection ratio test circuit.
1 VIN = 0.5 VPP 100 nF PULSE GEN. GND1 VPULSE = 5 V, fPULSE 1 kHz VCC1 100 nF GND1 5 6 7 8 2 k 2 3 4 Tx-en Tx-in Rx-PD-out Rx-Amp-in Status Rx-out VCC1 GND1 HCPL-810J GND2 Tx-out VCC2 Tx-PD-out Tx-LD-in Cext Rx-in Rref 16 15 14 13 12 11 1 F 10 100 nF 9 Rref 24 k GND2 VOUT 100 nF 100 F VCC2 GND2
Figure 15. Tx-PD-out enable/disable time test circuit.
VCC1 GND1 100 nF 2 k 1 2 3 4 5 6 VCC1 100 nF GND1 7 8 Tx-en Tx-in Rx-PD-out Rx-Amp-in Status Rx-out VCC1 GND1 HCPL-810J GND2 Tx-out VCC2 Tx-PD-out Tx-LD-in Cext Rx-in Rref 16 15 VOUT 50 RL 100 nF 100 nF GND2
14 1 F 13 12 11 10 9 Rref
VCC2 100 F
GND2 VIN = 1 VPP f = 10 k ~ 10 MHz
1 F 100 nF 24 k GND2
Figure 16. Line driver bandwidth test circuit.
12
Applications Information
Tx-en Tx-in C1 100 nF R1 5 k Rx-out Status R2 10 k VCC1 R3 2 k 100 nF 4 5 6 7 8 100 nF GND1 GND1 GND2 GND2 1 2 3 Tx-en Tx-in Rx-PD-out Rx-Amp-in Status Rx-out VCC1 GND1 HCPL-810J GND2 Tx-out VCC2 Tx-PD-out Tx-LD-in Cext Rx-in Rref 16 15 14 13 100 nF 12 11 10 9 Rref 24 k 1 F Filter GND2 Filter 1 F D1 L1 330 H N X2 100 F GND2 GND2 L2 C2 L GND2 R4 2 VCC2
Figure 17. Schematic of HCPL-810J application for FSK modulation scheme.
Typical application for FSK modulation scheme The HCPL- 810J is designed to work with various transceivers and can be used with a variety of modulation methods including ASK, FSK and BPSK. Figure 17 shows a typical application in a powerline modem using Frequency Shift Keying (FSK) modulation scheme. Transmitter The analogue Tx input pin is connected to the modulator via an external coupling capacitor C1 and a series resistor R3 (see Figure 17). Optimal performance is obtained with an input signal of 250 APP. E.g., for a modulator with an output signal of 0.5 VPP using a coupling capacitor of 100 nF, the optimal series resistor R3 would be 2 k. Tx AGC To ensure a stable and constant output voltage at Tx- PD- out, the HCPL- 810J includes an Automatic Gain Control (AGC) circuit in the isolated transmit signal path.
This AGC circuit compensates for variations in the input signal level presented at Tx- in and variations in the optical channel over temperature and time. The Tx- PD- out output signal is effectively stabilized for input Tx- in signals of between 150 APP and 250 APP (see Figure 8). The AGC circuit starts to function 10 s after the Tx- en signal is set to logic high. After a period of 180 s the Tx- PDout signal typically reaches 66% of its steady state level (see Figure 18). To ensure correct operation of the internal circuitry, an external 1 F capacitor needs to be connected from pin 11 to GND2.
The optical signal coupling technology used in the HCPL810J transmit path achieves very good harmonic distortion, which is usually significantly better than the distortion performance of the modulated input signal. However to meet the requirements of some international EMC regulations it is often necessary to filter the modulated input signal. The optimal position for such a filter is between pins 13 and 12 as shown in Figure 17. A possible band- pass filter topology is shown in Figure 19, some typical values of the components in this filter are listed in Table 1.
5 0 s/Div Tx-en 5 V/Div
Tx-PD-out 1 V/Div
ts, Tx tAGC
Figure 18. Tx-PD-out AGC response time.
13
R5 Filter input L3 C3 Filter output
Tx Rx 1F
L2
C2 L X2 L1 N
GND2
GND2
Figure 19. An example of a band-pass filter for transmit.
Figure 20. LC coupling network.
To compensate for the attenuation in the filter, the line driver stage has 6 dB gain. To prevent the line driver output from saturating, it is therefore important to achieve 6 dB of attenuation between Tx- PD- out (pin 13) and Tx- LD- in (pin 12) either by the inherent filter attenuation or by other means. Transmitter Line Driver The line driver is capable of driving powerline load impedances with output signals up to 4 VPP. The internal biasing of the line driver is controlled externally via a resistor Rref connected from pin 9 to GND2. The optimum biasing point value for modulation frequencies up to 150 kHz is 24 k. For higher frequency operation with certain modulation schemes, it may be necessary to reduce the resistor value to enable compliance with international regulations.
The output of the line driver is coupled onto the powerline using a simple LC coupling circuit as shown in Figure 20. Refer to Table 1 for some typical component values. Capacitor C2 and inductor L1 attenuate the 50/60 Hz powerline transmission frequency. A suitable value for L1 can range in value from 200 H to 1 mH. To reduce the series coupling impedance at the modulation frequency, L2 is included to compensate the reactive impedance of C2. This inductor should be a low resistive type capable of meeting the peak current requirements. To meet many regulatory requirements, capacitor C2 needs to be an X2 type. Since these types of capacitors typically have a very wide tolerance range of 20%, it is recommended to use as low Q factor as possible for the L2/C2 combination. Using a high Q coupling circuit will result in a
wide tolerance on the overall coupling impedance, causing potential communication difficulties with low powerline impedances. Occasionally with other circuit configurations, a high Q coupling arrangement is recommended, e.g., C2 less than 100 nF. In this case it is normally used as a compromise to filter out of band harmonics originating from the line driver. This is not required with the HCPL- 810J. Although the series coupling impedance is minimized to reduce insertion loss, it has to be sufficiently large to limit the peak current to the desired level in the worst expected powerline load condition. The peak output current is effectively limited by the total series coupling resistance, which is made up of the series resistance of L2, the series resistance of the fuse and any other resistive element connected in the coupling network. To reduce power dissipation when not operating in transmit mode the line driver stage is shut down to a low power high impedance state by pulling the Tx- en input (pin 1) to logic low state. The high impedance condition helps minimize attenuation on received signals.
Table 1. Typical component values for band-pass filter and LC coupling network. Carrier Frequency (kHz) 110 120 132 150 Band-Pass Filter L3 (H) 680 680 680 680 C3 (nF) 3.3 2.7 2.2 1.8 LC Coupling L2 (H) 15 10 6.8 6.8 C2 (nF) 150 220 220 220
14
Receiver The received signal from the powerline is often heavily attenuated and also includes high level out of band noise. Receiver performance can be improved by positioning a suitable filter prior to the Rx- in input (pin 10). To counter the inevitable attenuation on the powerline, the HCPL- 810J receiver circuit includes a fixed 20 dB front- end gain stage. If desired, this fixed gain can be reduced to unity gain by inserting an impedance of 33 k in the receiver signal path. It is however recommended to maintain the fixed gain of 20 dB at this position and reduce the overall signal gain elsewhere if required. This configuration will result in the best SNR and IMRR. The optical isolated Rx signal appears at Rx- PD- out (pin 3). This signal is subsequently AC coupled to the final gain stage via a capacitor. The final gain stage consists of an op- amp configured in an inverting configuration and DC biased at 2.27 V. The actual gain of this gain stage is user programmable with external resistors R1 and R2 as shown in Figure 17. The signal output at Rx- out (pin 6) is buffered and may be directly connected to the demodulator or ADC, using AC coupling if required. Internal Protection and Sensing The HCPL- 810J includes several sensing and protection functions to ensure robust operation under wide ranging environmental conditions. The first feature is the VCC2 Under Voltage Detection (UVD). In the event of VCC2 dropping to a voltage less than 4 V, the output status pin is switched to a logic low state. The next feature is the overtemperature shutdown. This particular feature protects the line driver stage from overtemperature stress. Should the IC junction temperature reach a level above 130C, the line driver circuit is shut down, simultaneously the output of Status (pin 5) is pulled to the logic low state. The final feature is load detection function. The powerline impedance is quite unpredictable and varies not just at different connection points but is also time variant. The HCPL- 810J includes a current sense feature, which may be utilized to feedback information on the instantaneous powerline load condition. Should the peak current reach a level greater than 0.6 APP, the output of Status pin is pulled to a logic low state for the entire period Table 2. Status pin logic output. Mode Receiver Mode Transmitter Mode Normal VCC2 < 4V High High Low Low Over-Temperature ITx-out < -0.3 A Low Low (pulsed) the peak current exceeds - 0.3 A, as shown in Figure 21. Using the period of the pulse together with the known coupling impedance, the actual powerline load can be calculated. Table 2 shows the logic output of the Status pin. External Transient Voltage Protection To protect the HCPL- 810J from high voltage transients caused by power surges and disconnecting/connecting the modem, it is necessary to add an external 6.8 V bi- directional transient voltage protector (as component D1 shown in Figure 17). Additional protection from powerline voltage surges can be achieved by adding an appropriate Metal Oxide Varistor (MOV) across the powerline terminals after the fuse.
Tx-out (pin 15) 0.5 A/Div
2 s/Div
Ith
tth
Status (pin 5) 2 V/Div tth
Figure 21. Transmit output load detection.
15
78L05 5V VOUT GND VIN
+ C* 470 H 120 mA 630 mA L X2 1.5 F/3.3 F 1000 F 9.1 V 1 W VARISTOR 220 kU N
100 nF
* 1.5F X2 for 230V mains, 3.3F X2 for 110V mains
GND2
Figure 22. A simple low cost non-isolated power supply.
VCC2 Power Supply Requirements The recommended voltage regulator to supply VCC2 is a low cost 78L05 or equivalent. To minimize harmonic distortion, it is recommended to connect a tantalum decoupling capacitor of at least 10 F together with a 100 nF ceramic capacitor in parallel. The capacitors should be positioned as close as possible to the supply input pin. The supply voltage for the regulator can be supplied from the system level power supply transformer (powerline side winding). Alternatively, the supply can be derived directly from the powerline via a simple low cost circuit as shown in Figure 22.
Thermal Considerations The high efficiency line driver used in the HCPL- 810J ensures minimum internal power dissipation, even for high peak output currents. Despite this, operating the line driver continuously with high output currents at elevated ambient temperatures can cause the peak junction temperature to exceed 125C and/or resulting in the triggering of the thermal protection. To prevent this from happening, when operating the line driver continuously with high output currents, an ambient temperature derating factor
1.4
MAXIMUM POWER DISSAPATION - W
needs to be applied. A typical derating curve is shown in Figure 23. In this case the assumption is that the transmitter is operating continuously in still air with a typical 2- layer Printed- Circuit Board (PCB). However, it should be noted that operating the transmitter discontinuously for short periods of time will allow lower derating or even no derating at all. Conversely operating the line driver continuously with a poor PCB layout and/or with restricted air convection could result in the requirement for a larger derating factor.
1.2 1 0.8 0.6 0.4 0.2 0 -40 -
-15 -
10
35
60
85
TA - AMBIENT TEMPERATURE - C
Figure 23. Power derating vs. temperature.
www.agilent.com/semiconductors
For product information and a complete list of distributors, please go to our web site. Data subject to change. Copyright 2003 Agilent Technologies, Inc. March 18, 2004 5989-0717EN

▲Up To Search▲

Price & Availability of HCPL-810J

	To Download HCPL-810J Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .